The present invention relates generally to computer memory, and more specifically to program disturb error logging and correction in not-and (NAND) flash memory.
Phase-change memories (PCMs) and flash memories are examples of non-volatile memories with limited endurance (also referred to as a “limited life”). Such memories have limited endurance in the sense that after undergoing a number of writing cycles (RESET cycles for PCM, program/erase cycles for flash memory), the memory cells wear out and may no longer be able to reliably store information. In addition, flash memory may be affected by errors in surrounding pages that are introduced while writing data to a page. These types of errors are referred to as disturb errors.
Contemporary NAND flash memory devices do not support page level erases. The absence of page erases, implies that once a page is written, it cannot be rewritten until the entire block (e.g., made up of sixty-four pages) is erased. If a logical address corresponding to a page needs to be refreshed, this is accomplished by marking the page as invalid and mapping the logical block address to a different physical page. Disturb errors, however, may cause the bits of the erased pages to appear to be written (i.e. changed from ‘1’ to ‘0’. Because individual pages cannot be erased, disturb errors in blank pages may cause faulty values in data that is subsequently written to those pages.
In addition, disturb errors in memory may affect previously written pages by flipping bits from the programmed value to a new value. Typically these errors are undetectable and only manifest themselves once the data is read from memory. Error correction codes may be used to protect data stored in NAND flash devices. Though suited for their intended purpose, these correction codes, however, may not be able to correct disturb errors properly and/or efficiently.